The race to improve computer performance has taken a new turn. Researchers at the University of Illinois have developed a way to stack multiple layers of silicon electronics on top of each other, a breakthrough that could help the semiconductor industry move past the limits of conventional chip design.
The study, published in Nature, demonstrates a method that delivers high-performance silicon devices with manufacturing yields of 98% to 100%. Researchers say the technology could eventually fit into commercial chip production.
For decades, the semiconductor industry increased computing power by shrinking transistors and placing more of them on a chip. That strategy followed Moore’s law and drove rapid advances in processors.
Engineers now face growing challenges as transistors approach atomic scales. Physical limits of silicon and quantum effects are making further miniaturisation increasingly difficult.
Researchers are exploring vertical integration as an alternative. Instead of squeezing more components onto a flat surface, circuits can be stacked in layers. This approach increases device density and shortens communication paths inside a chip.
Three-dimensional chip designs already exist in commercial products. Most are built by bonding separate wafers together. These designs improve performance, though connections between layers remain limited.
Monolithic 3D integration takes a different route. Each layer is built directly on top of an existing circuit. The concept offers far denser connections and faster data movement.
The biggest challenge has been heat. Traditional silicon manufacturing often requires temperatures near 1,000 degrees Celsius. Existing circuitry cannot survive such conditions.
The Illinois team developed ultrathin silicon nanomembranes that can be transferred onto completed circuits at temperatures below 200 degrees Celsius. The process preserves the quality of single-crystal silicon while staying within industry thermal limits.
Researchers built three stacked layers containing 625 transistors each and connected them through vertical metal links. They successfully demonstrated 3D logic circuits and memory cells.
The transistors matched the performance of conventional silicon devices and outperformed alternative low-temperature materials by three to four times.
The team stated the process can support additional layers in future designs. Industry partners involved in the research programme include IBM, Intel and Taiwan Semiconductor Manufacturing Company, highlighting growing interest in next-generation chip architectures.
The breakthrough arrives at a time when chipmakers are searching for new ways to increase computing power without relying entirely on smaller transistors. If the technology proves scalable in commercial foundries, it could open the door to faster processors, more efficient AI hardware and denser memory systems. The research also suggests that the next chapter of semiconductor innovation may come from building upward rather than shrinking further.
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