Samsung has reportedly developed the world’s first 900-layer-class V-NAND flash memory prototype using advanced stacking technology. The development pushes the semiconductor industry closer to the highly anticipated 1,000-layer NAND era. Samsung was the first company in the world to commercialize 3D V-NAND flash chips in 2013. The company initially used a manufacturing process that involved drilling and stacking microscopic holes in a single step.
Samsung has created the world’s first 900-layer V-NAND flash storage chip prototype. At a time when AI growth is driving massive demand for DRAM and NAND flash memory. The prototype reportedly uses a technology called Cell Multi-Bonding (CMB), which fuses two 450-layer cell wafers into a single chip.
Stacking multiple NAND flash layers improves storage density while reducing power consumption. Such high-density stacked structures are increasingly considered advantageous for AI computing workloads.
Samsung reportedly encountered challenges such as wafer warping and stack misalignment. The company addressed those issues using an advanced Upper Chuck design and Overlay Correction technology.
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SK Hynix is currently regarded as a leader in the high-layer NAND storage segment with its 321-layer NAND chips. However, Samsung appears to be in a strong position by simultaneously readying for the mass production of 400-layer tenth-generation NAND flash chips while also reaching the 900-layer milestone during the research phase.
Samsung has also reportedly improved the Bitline (BL) and Wordline (WL) structures, significantly reducing both power consumption and chip size. Early last year, Samsung unveiled its 10th-generation V-NAND technology. The company also introduced hybrid bonding, indicating that the technology has since been refined.
Chinese company Yangtze Memory Technologies Co. (YMTC) is rapidly narrowing the gap with Samsung and SK Hynix in the NAND flash market. YMTC has already begun mass production of 294-layer NAND chips, supported by substantial Chinese government investment and increased localization of chip manufacturing equipment.